Cohort: 2 

Locations: Santa Clara & Sunnyvale, United States 

Application Title: Reinforcement learning, generative AI and agentic AI for chip design

Application Subtitle: A design framework that applies reinforcement learning and agent-based systems within existing EDA tools to coordinate simulations, reduce manual execution work, and support complex chip design under tight time and talent constraints. 

Team Members

Synopsys: Shankar Krishnamoorthy (executive sponsor), Thomas Andersen, Arun Venkatachar, Anand Thiruvengadam

AMD: Mydung Pham, Rajit Seahra. 

The challenge 

Designing modern semiconductor chips has become increasingly complex. Chips must deliver higher performance and better energy efficiency, even as design timelines shorten and engineering teams remain constrained. At the same time, the global shortage of semiconductor engineers is expected to widen over the coming decade. 

Chip design relies on electronic design automation (EDA) tools. These tools help engineers translate high-level specifications into detailed circuit layouts, then verify that designs meet performance, power and reliability requirements. While EDA tools are highly capable, they are typically driven through long sequences of manual steps. Engineers configure tools, run simulations, review results and adjust parameters repeatedly until designs are ready for signoff. 

This approach is proven, but it is time-intensive. It requires sustained expert attention and significant computing resources. As designs grow more complex, late-stage changes become harder to manage and more costly to correct. 

The solution 

Goal-driven assistance within existing design environments 

AMD and Synopsys are working together to introduce AI-supported workflows that assist engineers throughout the chip design process. 

Rather than replacing existing EDA tools, the approach embeds intelligent systems directly into the environments engineers already use. These systems interpret design goals, coordinate tool runs and evaluate intermediate results. Engineers remain responsible for decisions, while routine execution tasks are handled automatically. 

By shifting from manual tool operation to goal-driven workflows, teams can reduce repetitive effort. This allows engineers to focus on architectural choices and trade-offs while maintaining full visibility into the design process. 

How it works 

Learning from real design activity 

The system uses components capable of reasoning about design objectives and planning sequences of actions across the toolchain. It learns from historical design data as well as from interactions with engineers during active projects. 

Training draws on years of internal design experience from AMD and the capabilities of Synopsys’ EDA platforms. Over time, the system can recognize recurring design patterns and flag potential issues earlier in the flow. It can also help engineers explore alternative design options more efficiently. 

This support improves iteration speed while keeping human designers in control of key decisions. 

How it differs from conventional approaches 

Reducing manual orchestration 

Traditional chip design workflows require engineers to manually orchestrate each step of the EDA process. Adjustments are often reactive, based on results that appear late in the cycle. 

AMD and Synopsys’ approach reduces reliance on manual coordination by allowing AI-supported systems to manage execution across tools. Engineers set objectives and constraints, then review and refine outcomes as the system progresses through the workflow. 

This helps identify potential issues earlier and reduces the likelihood of disruptive late-stage changes. 

Impact 

• Productivity across design and verification stages approximately doubled 
• Design exploration expanded by 25%, allowing teams to evaluate a wider range of options 
• Overall design costs reduced by a factor of five 
• Time to signoff reduced by 50%, with fewer late-cycle changes 
• Faster design cycles contributing to improved reliability and fewer defects 

Why it matters 

Making expert time go further 

As chip complexity continues to increase, design productivity depends on how effectively expert engineers can focus their attention. The collaboration between AMD and Synopsys shows how AI-supported workflows can help teams make better use of limited expertise without changing established tools or processes. 

By supporting engineers throughout the design flow, this approach helps shorten development cycles and manage complexity in an industry where both time and talent are increasingly constrained.